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an - 0 64e rev.1. 3 a pril 201 2 1 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / fuji switching power supply control ic green mode quasi - resonant ic fa5 640 /41/42 /43/44 /48 application note a pril 20 1 2 fuji electric co., ltd.
an - 0 64e rev.1. 3 a pril 201 2 2 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / 1. the contents of this note (product specification, charac teristics, data, materials, and structure etc.) were prepared in a pril 20 1 2 . the contents will subject to change without notice due to product specification change or some other reasons. in case of using the products stated in this document, the latest p roduct specification shall be provided and the data shall be checked. 2. the application examples in this note show the typical examples of using fuji products and this note shall neither assure to enforce the industrial property including some other ri ghts nor grant the license. 3. fuji electric co.,ltd. is always enhancing the product quality and reliability. however, semiconductor products may get out of order in a certain probability. measures for ensuring safety, such as redundant design, spreading fire protection design, malfunction protection design shall be taken, so that fuji electric semiconductor product may not cause physical injury, property damage by fire and social damage as a result. 4. products described in this note are manufactured an d intended to be used in the following electronic devices and electric devices in which ordinary reliability is required: - computer - oa equipment - communication equipment ( pin ) - measuring equipment - machine tool - audio visual equipment - home appliance - personal equipment - industrial robot etc. 5. customers who are going to use our products in the following high reliable equipments shall contact us surely and obtain our consent in advance. in case when our products are used in the followi ng equipment, suitable measures for keeping safety such as a back - up - system for malfunction of the equipment shall be taken even if fuji electric semiconductor products break down: - transportation equipment (in - vehicle, in - ship etc.) - communication equ ipment for trunk line - traffic signal equipment - gas leak detector and gas shutoff equipment - disaster prevention/security equipment - various equipment for the safety. 6. products described in this note shall not be used in the following equipmen ts that require extremely high reliability: - space equipment - aircraft equipment - atomic energy control equipment - undersea communication equipment - medical equipment. 7. when reprinting or copying all or a part of this note, our company s accep tance in writing shall be obtain ed . 8. if obscure parts are found in the contents of this note, contact fuji electric co.,ltd. or a sales agent before using our products. fuji electric co.,ltd. and its sales agents shall not be liable for any damage that is caused by a customer who does not follow the instructions in this cautionary statement. caution
an - 0 64e rev.1. 3 a pril 201 2 3 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / contents 1. overview ????????????????? 4 2. features ????????????????? 4 3. outline drawing s ????????????????? 4 4. block diagram ????????????????? 5 - 7 5. functional description of pins ????????????????? 8 6. rating and characteristics ????????????????? 8 - 1 3 7. characteristic curve ????????????????? 1 4 - 1 8 8. basic operation ????????????????? 1 9 9. description of the function ????????????????? 20 - 2 6 10. how to use pin and advice designing ? ??????????? ??? 27 - 3 6 1 1 . precautions for pattern design ????????? ???????? 3 7 1 2 . example of application circuit ????????????????? 3 8 caution) ? the contents of this note will subject to change without notice due to improvement. ? the application examples or the components constants in this note are shown to help your design, and variation of components and service conditions are not taken into account. in using these components, a design with due consideration for these conditions shall be conducted.
an - 0 64e rev.1. 3 a pril 201 2 4 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / 1. overview fa5 640 series are a q uasi - r esonant type switching power supply control ic with excellent stand - by characteristics. though it is a small package with 8 pins, it has a lot of functions and enables to decrease external parts. therefore it is possible to realize a small size an d a high cost - performance power supply. 2. features ? a quasi - resonant type switching power supply ? a power supply with excellent standby characteristics ? low power consumption achieved by integrated startup circuit ? low current consumption, during operation: 0. 85 ma ? control of num ber of bottom skips by on - off width detection ? burst operation function under light load ? built - in drive circuit directly connectable to a power mosfet, output current: 0.5 a (sink)/0.25 a (source) ? built - in o verload protection function ? built - in latch protection function based on overvoltage detection on the secondary side ? m aximum input threshold voltage of is pin and threshold voltage of stopping on - pulse are compensated by detecting high - line voltage . ? built - in under voltage lock out function, on threshold voltage: 14 v and 10 v ? package: sop - 8 function list by types type overload protection on threshold voltage o peration compens ation minimum switching frequency delay time of restart is pin one shot latch function changing of overload protection levels due to external signal detection change point from 1st bottom to 2nd bottom fa5640 auto recovery 14v yes no 25us no yes 110khz fa5641 auto recovery 14v yes 25khz 7.6 us no yes 110khz fa5542 auto recovery 10v no no 25us no yes 110khz fa554 3 auto r ecovery 14v yes 25khz 25us yes no 110khz fa554 4 timer latch 14v yes no 25us no yes 110khz fa554 8 auto recovery 14v yes no 1 2 . 5us no no 260khz (speeding up) 3. o utline drawings sop - 8 0 . 6 5 0 . 2 5 0 1 0 3 . 9 0 . 2 1 . 8 m a x 1.27 5.00.25 1 pin mark 0 . 2 0 . 1 0.40.1 0 . 2 6 . 0 0 . 3
an - 0 64e rev.1. 3 a pril 201 2 5 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / 4 . block diagram fa5 640 fa5 641 b o t t o m d e t e c t i o n s r 1 q s t a r t u p c u r r e n t u v l o v h v c c 4 . 8 v r e g . i n t e r n a l s u p p l y d r i v e r o u t s t a r t u p m a n a g e m e n t 1 1 v / 9 v 3 . 5 / 3 . 3 v o v e r l o a d 1 4 v / 8 v e n b g n d f b i s z c d t i m e r 2 0 0 m s 1 6 0 0 m s d i s a b l e s o f t s t a r t ( 1 m s ) c u r r e n t c o m p a r a t o r 4 . 8 v 4 . 8 v 1 / 6 1 0 a l a t c h t i m e r 6 0 s z c d o v p 1 o f f t i m e r ( 4 . 5 s ) l a t c h p r o t e c t i o n 6 v o v p d e t e c t i o n z c d e n b o l p p r o t e c t i o n r e s e t o f f t i m e r ( 2 s ) r 2 i n p u t v o l t a g e d e t e c t i o n m o d e s e l e c t s i g n a l v i n h 2 4 k r e s i s t a n c e r a t i o m p 1 o n / o f f 9 1 . 3 % / 1 0 0 % 8 4 . 1 % / 1 0 0 % 3 0 k 7 . 5 v 1 s h o t ( 2 9 0 n s ) e n b s e t b o t t o m s k i p c o n t r o l m a x . t o n ( 2 4 s ) r e s e t p u l s e w i d t h d e t e c t i o n 0 . 5 v v i n h 0 . 4 5 v v t h i s r e s t a r t t i m e r 2 5 s 0 . 4 5 v v i n h 0 . 3 5 v v t h f b 0 0 . 5 5 v s t a n d b y s t a n d b y d e t e c t i o n + - 1 5 0 k v i n h 0 . 1 5 v v i n h 0 . 1 0 v v t h i s a t s t a n d b y m p 1 b o t t o m d e t e c t i o n s r 1 q s t a r t u p c u r r e n t u v l o v h v c c 4 . 8 v r e g . i n t e r n a l s u p p l y d r i v e r o u t s t a r t u p m a n a g e m e n t 1 1 v / 9 v 3 . 5 / 3 . 3 v o v e r l o a d 1 4 v / 8 v e n b g n d f b i s z c d t i m e r 2 0 0 m s 1 6 0 0 m s d i s a b l e s o f t s t a r t ( 1 m s ) c u r r e n t c o m p a r a t o r 4 . 8 v 4 . 8 v 1 / 6 1 0 a l a t c h t i m e r 6 0 s z c d o v p 1 o f f t i m e r ( 4 . 5 s ) l a t c h p r o t e c t i o n 6 v o v p d e t e c t i o n z c d e n b o l p p r o t e c t i o n r e s e t o f f t i m e r ( 2 s ) r 2 i n p u t v o l t a g e d e t e c t i o n m o d e s e l e c t s i g n a l v i n h 2 4 k r e s i s t a n c e r a t i o m p 1 o n / o f f 9 1 . 3 % / 1 0 0 % 8 4 . 1 % / 1 0 0 % 3 0 k 7 . 5 v 1 s h o t ( 2 9 0 n s ) e n b s e t b o t t o m s k i p c o n t r o l m a x . t o n ( 2 4 s ) r e s e t p u l s e w i d t h d e t e c t i o n 0 . 5 v v i n h 0 . 4 5 v v t h i s r e s t a r t t i m e r 7 . 6 s 0 . 4 5 v v i n h 0 . 3 5 v v t h f b 0 0 . 5 5 v s t a n d b y s t a n d b y d e t e c t i o n + - 1 5 0 k v i n h 0 . 1 5 v v i n h 0 . 1 0 v v t h i s a t s t a n d b y m p 1 m i n . f s w ( 2 5 k h z )
an - 0 64e rev.1. 3 a pril 201 2 6 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / fa5 642 fa5 643 b o t t o m d e t e c t i o n s r 1 q s t a r t u p c u r r e n t u v l o v h v c c 4 . 8 v r e g . i n t e r n a l s u p p l y d r i v e r o u t s t a r t u p m a n a g e m e n t 1 1 v / 9 v 3 . 5 / 3 . 3 v o v e r l o a d 1 0 v / 8 v e n b g n d f b i s z c d t i m e r 2 0 0 m s 1 6 0 0 m s d i s a b l e s o f t s t a r t ( 1 m s ) c u r r e n t c o m p a r a t o r 4 . 8 v 4 . 8 v 1 / 6 1 0 a l a t c h t i m e r 6 0 s z c d o v p 1 o f f t i m e r ( 4 . 5 s ) l a t c h p r o t e c t i o n 6 v o v p d e t e c t i o n z c d e n b o l p p r o t e c t i o n r e s e t o f f t i m e r ( 2 s ) r 2 2 4 k r e s i s t a n c e r a t i o m p 1 o n / o f f 9 1 . 3 % / 1 0 0 % 3 0 k 7 . 5 v 1 s h o t ( 2 9 0 n s ) e n b s e t b o t t o m s k i p c o n t r o l m a x . t o n ( 2 4 s ) r e s e t p u l s e w i d t h d e t e c t i o n 0 . 5 v v t h i s r e s t a r t t i m e r 2 5 s 0 . 4 5 v v t h f b 0 0 . 5 5 v s t a n d b y s t a n d b y d e t e c t i o n + - 1 5 0 k 0 . 1 5 v v t h i s a t s t a n d b y m p 1 b o t t o m d e t e c t i o n s r 1 q s t a r t u p c u r r e n t u v l o v h v c c 4 . 8 v r e g . i n t e r n a l s u p p l y d r i v e r o u t s t a r t u p m a n a g e m e n t 1 1 v / 9 v 3 . 5 / 3 . 3 v o v e r l o a d 1 4 v / 8 v e n b g n d f b i s z c d t i m e r 2 0 0 m s 1 6 0 0 m s d i s a b l e s o f t s t a r t ( 1 m s ) c u r r e n t c o m p a r a t o r 4 . 8 v 4 . 8 v 1 / 6 1 0 a l a t c h t i m e r 6 0 s z c d o v p 1 o f f t i m e r ( 4 . 5 s ) l a t c h p r o t e c t i o n 6 v o v p d e t e c t i o n z c d e n b o l p p r o t e c t i o n r e s e t r 2 i n p u t v o l t a g e d e t e c t i o n v i n m o d e s e l e c t s i g n a l v i n h 2 4 k r e s i s t a n c e r a t i o m p 1 o n / o f f 9 1 . 3 % / 1 0 0 % 8 4 . 1 % / 1 0 0 % 3 0 k 7 . 5 v 1 s h o t ( 2 9 0 n s ) e n b s e t b o t t o m s k i p c o n t r o l m a x . t o n ( 2 4 s ) r e s e t p u l s e w i d t h d e t e c t i o n 0 . 5 v v i n h 0 . 4 5 v v t h i s r e s t a r t t i m e r 2 5 s 0 . 4 5 v v i n h 0 . 3 5 v v t h f b 0 0 . 9 7 v l a t c h - o f f + - 1 5 0 k v i n h m p 1 m i n . f s w ( 2 5 k h z ) f a 5 6 4 3
an - 0 64e rev.1. 3 a pril 201 2 7 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / fa5 644 fa5 648 b o t t o m d e t e c t i o n s r 1 q s t a r t u p c u r r e n t u v l o v h v c c 4 . 8 v r e g . i n t e r n a l s u p p l y d r i v e r o u t s t a r t u p m a n a g e m e n t 1 1 v / 9 v 3 . 5 / 3 . 3 v o v e r l o a d 1 4 v / 8 v e n b g n d f b i s z c d t i m e r 2 5 6 m s d i s a b l e s o f t s t a r t ( 1 m s ) c u r r e n t c o m p a r a t o r 4 . 8 v 4 . 8 v 1 / 6 1 0 a l a t c h t i m e r 6 0 s z c d o v p 1 o f f t i m e r ( 4 . 5 s ) l a t c h p r o t e c t i o n 6 v o v p d e t e c t i o n z c d e n b o l p p r o t e c t i o n o f f t i m e r ( 2 s ) r 2 i n p u t v o l t a g e d e t e c t i o n v i n m o d e s e l e c t s i g n a l v i n h 2 4 k r e s i s t a n c e r a t i o m p 1 o n / o f f 9 1 . 3 % / 1 0 0 % 8 4 . 1 % / 1 0 0 % 3 0 k 7 . 5 v 1 s h o t ( 2 9 0 n s ) e n b s e t b o t t o m s k i p c o n t r o l m a x . t o n ( 2 4 s ) r e s e t p u l s e w i d t h d e t e c t i o n 0 . 5 v v i n h 0 . 4 5 v v t h i s r e s t a r t t i m e r 2 5 s 0 . 4 5 v v i n h 0 . 3 5 v v t h f b 0 0 . 5 5 v s t a n d b y s t a n d b y d e t e c t i o n + - 1 5 0 k v i n h 0 . 1 5 v v i n h 0 . 1 0 v v t h i s a t s t a n d b y m p 1 f a 5 6 4 4 t i m e r 2 5 6 m s 1 6 5 6 m s b o t t o m d e t e c t i o n s r 1 q s t a r t u p c u r r e n t u v l o v h v c c 4 . 8 v r e g . i n t e r n a l s u p p l y d r i v e r o u t s t a r t u p m a n a g e m e n t 1 1 v / 9 v 3 . 5 / 3 . 3 v o v e r l o a d 1 4 v / 8 v e n b g n d f b i s z c d d i s a b l e s o f t s t a r t ( 1 m s ) c u r r e n t c o m p a r a t o r 4 . 8 v 4 . 8 v 1 / 6 1 0 a l a t c h t i m e r 6 0 s z c d o v p 1 o f f t i m e r ( 1 s ) l a t c h p r o t e c t i o n 6 v o v p d e t e c t i o n z c d e n b o l p p r o t e c t i o n r e s e t o f f t i m e r ( 5 3 0 n s ) r 2 i n p u t v o l t a g e d e t e c t i o n v i n m o d e s e l e c t s i g n a l v i n h 2 4 k r e s i s t a n c e r a t i o m p 1 o n / o f f 9 1 . 3 % / 1 0 0 % 8 4 . 1 % / 1 0 0 % 3 0 k 7 . 5 v 1 s h o t ( 1 4 0 n s ) e n b s e t b o t t o m s k i p c o n t r o l m a x . t o n ( 9 s ) r e s e t p u l s e w i d t h d e t e c t i o n 0 . 5 v v i n h 0 . 4 5 v v t h i s r e s t a r t t i m e r 1 2 . 5 s 0 . 4 5 v v i n h 0 . 3 5 v v t h f b 0 + - 1 5 0 k v i n h m p 1 f a 5 6 4 8
an - 0 64e rev.1. 3 a pril 201 2 8 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / 5 . functional description of pins pin number pin name pin function 1 zcd zero c urrent d etec tion , ovp detection 2 fb feedback i nput, olp detection , burst operation control 3 is current s ense i nput, over - current l imiter , standby signal detection 4 gnd ground 5 out output 6 vcc power supply, uvlo , vh pin current control 7 ( n . c .) no c onnection 8 vh high v oltage i nput 6 . rating and characteristics * + shows sink and C shows source in current prescription. (1) absolute maximum rating s item symbol rating unit supply voltage vcc 28 v peak current at out pin (note 1) ioh - 0.25 a i ol +0.5 a the voltage at out pin v out - 0.3 to vcc+0.3 v input voltage at fb and is pin vfb, vis - 0.3 to 5.0 v the current at fb and is pin ifb, iis - 0.3 to + 0.3 ma the current at zcd pin isozcd - 2.0 ma isizcd +3.0 ma the voltage at zcd pin vzcd - 2 to + 8 v input voltage at vh pin vvh - 0.3 to 500 v power d issipation ta=25 pd 400 mw operating j unction t emperature tj - 40 to +125 storage t emperature tstg - 40 to +150 note 1 ) please consider power supply voltage and load curre nt well and use this ic within m aximum p ower dissipation , operating junction temperature and r e commended ambient temperature in operation . the ic may cross over maximum power dissipation at normal operating condition by power supply voltage or load current within peak current absolute maximum rating . * allowable loss reduction characteristi cs package thermal resistor 400 S?p? maximum dissipation pd [mw] 25 85 125 ?? ambiance temperature ta [ ] - 4 0 0
an - 0 64e rev.1. 3 a pril 201 2 9 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / (2) recommended operating condition s item symbol min . typ. max . unit supply v oltage vcc 11 15 2 6 v input v oltage at vh pin vvh 50 450 v capacitance at vcc pin cvcc 10 47 220 uf turn - off resonant period trs 2 4 us ambi e nt temperatur e in operation ta - 40 85 (3) dc electric characteristics (unless otherwise specified : v cc =15v, vh= 141 v, zcd=0v, fb=3v, is=open, tj=25 ) current sens e part (is pin) item symbol conditions min. typ. max. unit input bias current iis v is =0v - 15 - 1 0 - 5 ua maximum threshold voltage vthis 1 vfb =3 .2 v , vvh=141v 0. 47 0 .5 0.53 v vthis 2 fa5640 / 41 /43/44 /48 vfb=3.2v, v vh =324v 0.42 0.45 0.48 v voltage gain avis v /v k k k k S S S S
an - 0 64e rev.1. 3 a pril 201 2 10 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / zero current detection part (zcd pin) item sym bol conditions min. typ. max. unit input threshold voltage vthzcd1 vzcd decreasing 40 60 80 mv vthzcd2 v zcd increasing 1 0 0 1 50 22 0 mv hysteresis vhyzcd v thzcd2 - vthzcd1 30 90 15 0 mv minimum detectable pulse width tzcdmin zcd input pulse vpulse=1v to 0v f =100khz 3 00 k
an - 0 64e rev.1. 3 a pril 201 2 11 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / ov erload protection part (fb pin) item sym bol conditions min. typ. max. unit olp threshold voltage volp1 v fb increasing 3.3 3.5 3.8 v volp2 v fb decreasing 3.0 3.3 3.6 v hysteresis hysolp volp1 - volp2 0.1 0.2 0.3 v fault time duration tolp fa5640/41/42/43 delay from v fb >volp1 1 40 20 0 2 60 m s FA5644 delay from v fb >volp1 1 95 256 320 m s fa5648 delay from v fb >volp1 200 256 333 m s auto recovery mode latch - off time duration toff fa5640/41/42/43 t he off time only by internal signal 980 1400 1820 ms soft start part item sym bol conditions min. typ. max. unit soft - start time tsoft at start - up only 0.7 1.0 1.3 m s standby - mode function ( is pin ) (fa5640,fa5641,fa5642,FA5644) item sym bol conditions min. typ. max. unit stand - by detection threshold vo ltage at is pin visstb read timing is turn - off after tstb. 0.5 0.55 0.6 v stand - by detection timing tstb delay from turn - off 1.5 2.0 2.5 us maximum threshold voltage at stand - by vthis s
an - 0 64e rev.1. 3 a pril 201 2 12 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / high voltage input part (vh pin) item symbol condition min. typ. max. unit supply current of vh pin ivhrun v vh =400v, v cc > vstoff 10 30 60 ua ivh1 v vh =100v, vcc=6.5v 4.0 8 .0 10.5 ma ivh0 v vh =100v, vcc=0v 0. 49 0.7 1.4 ma charge current for vcc pin ipre1 v cc =8v, v vh =100v - 10 - 7 .4 - 3.7 ma ipre2 v cc =1 3 v, v vh =100v a t uvlo mode - 9 - 5 . 7 - 3 ma t h e threshold voltage to change input voltage mode setting at dc input vhdch fa5640/41 / 43 / 44 /4 8 vcc>vstoff vh pin input voltage is increasing by dc voltage. 200 226 250 v vhdcl fa5640/41 / 43 / 44 /48 vcc>vstoff vh pin input voltage is decreasing by dc voltage. 190 212 235 v hysteresis voltage width at dc input only vhdchys fa5640/41 / 43 / 44 /48 vh: dc voltage input vhdch - vhdcl 8 14 18 v t h e threshold voltage to change input voltage mode setting at ac input (ac rms conversion voltage) vhac fa5640/41 / 43 / 44 /48 v cc >vstoff vh pin input voltage is half - wave rectified ac wave form. 141 160 177 vrms delay time of changing input voltage mode setting tpdvh fa5640/41 / 43 / 44 /48 vcc>vstoff (vcc charge off) 11 30 70 ms low voltage malfunction protection circuit (uvlo) part (vcc pin) item symbol condition min. typ. max. unit start - up threshold voltage vccon fa5640/41 / 43 / 44 /48 v cc increasing 1 2.5 1 4 15.5 v fa5642 v cc increasing 9 10 11 v shutdown threshold voltage vccoff v cc decreasing 7 8 9 v hysteresis (uvlo) vhys1 fa5640/41 / 43 / 44 /48 vccon - vccoff 5 6 7 v istart - up off voltage fa5642 vccon - vccoff 1.5 2 2.5 v istart - up restart voltage vstoff v cc increasing 9.5 1 1 12 .5 v hysteresis width at ist art - up vstrst v cc decreasing 8 9 10 v
an - 0 64e rev.1. 3 a pril 201 2 13 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / current consumption (vcc pin) item symbol condition min. typ. max. unit operating - state supply current iccop1 fa5640/41/42/44/48 vfb =2v, is= open vzcd=0v out= no load fa564 3 vfb =2v, is= 0.75 vzcd=0v o ut= no load 0. 7 0.85 1.5 ma iccop2 fa5640/41 / 4 2/ 44 /48 duty cycle=0%, vfb =0v , is=open vzcd=0v fa564 3 duty cycle=0%, vfb =0v , is=0.75 vzcd=0v 0.6 0.8 1. 1 ma latch mode supply cu r rent icclat fb=open v cc =11v a t latch - mode 10 0 2 00 3 50 ua *1 : regarding to these items, guaranteed by design . the column showing - has no specified value.
an - 0 64e rev.1. 3 a pril 201 2 14 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / 7 . characteristic curve ? unless otherwise specified : t j = 25 , v cc=15v ? + shows sink and C shows source in current prescription. ? data listed here shows the typical characteristics of an ic and does not guarantee the characteristics. is pin maximum threshold voltage (vthis1) vs. junction temperature (tj) 0.47 0.48 0.49 0.5 0.51 0.52 0.53 -50 -25 0 25 50 75 100 125 150 tj [] vthis1 [v] is pin maximum threshold voltage (vthis2) vs. junction temperature (tj) 0.42 0.43 0.44 0.45 0.46 0.47 0.48 -50 -25 0 25 50 75 100 125 150 tj [] vthis2 [v] fb pin input threshold voltage switching off (vthfb01) vs. junction temperature(tj) 400 410 420 430 440 450 460 470 480 490 500 -50 -25 0 25 50 75 100 125 150 tj [] vthfb01 [mv] fb pin input threshold voltage switching off (vthfb02) vs. junction temperature (tj) 315 325 335 345 355 365 375 385 -50 -25 0 25 50 75 100 125 150 tj [] vthfb02 [mv] is pin maximum threshold voltage (vthis1) vs. fb pin voltage (vfb) 0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 vfb [v] vthis1 [v]
an - 0 64e rev.1. 3 a pril 201 2 15 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / zcd pin input threshold voltage (vthzcd2) vs. junction temperature (tj) 100 120 140 160 180 200 220 -50 -25 0 25 50 75 100 125 150 tj [] vthzcd2 [mv] zcd pin internal resistance (rzcd) vs. junction temperature (tj) 22.5 25 27.5 30 32.5 35 37.5 -50 -25 0 25 50 75 100 125 150 tj [] rzcd [k ] zcd pin ovp threshold voltage (vovp) vs. junction temperature (tj) 5.7 5.8 5.9 6 6.1 6.2 6.3 -50 -25 0 25 50 75 100 125 150 tj [] vovp [v] delay time to olp (tolp) vs. junction temperature (tj) 140 160 180 200 220 240 260 -50 -25 0 25 50 75 100 125 150 tj [] tolp [ms] zcd pin input threshold voltage (vthzcd1) vs. junction temperature (tj) 20 30 40 50 60 70 80 -50 -25 0 25 50 75 100 125 150 tj [] vthzcd1 [mv] delay time to olp (tolp) vs. junction temperature (tj) 190 210 230 250 270 290 310 -50 -25 0 25 50 75 100 125 150 tj () tolp (ms) FA5644/48 vfb volp1
an - 0 64e rev.1. 3 a pril 201 2 16 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / input current of vh pin (ivhrun) vs. junction temperature (tj) 10 15 20 25 30 35 40 45 50 55 60 -50 -25 0 25 50 75 100 125 150 tj [] ivhrun [ua] input current of vh pin (ivh) vh pin voltage (vvh) 0 1 2 3 4 5 6 7 8 9 10 0 100 200 300 400 500 vvh [v] ivh [ma] olp off time (toff) vs. junction temperature (tj) 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 -50 -25 0 25 50 75 100 125 150 tj [] toff [ms] is pin maximum threshold voltage at standby (vthisst1) vs. junction temperature (tj) 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 -50 -25 0 25 50 75 100 125 150 tj [] vthisst1 [v] is pin maximum threshold voltage at standby (vthisst2) vs. junction temperature (tj) 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 -50 -25 0 25 50 75 100 125 150 tj [] vthisst2 [v]
an - 0 64e rev.1. 3 a pril 201 2 17 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / input current of vh pin (ivh1) vs. junction temperature (tj) 4 5 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 150 tj [] ivh1 [ma] input current of vh pin (ivh0) vs. junction temperature (tj) 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -50 -25 0 25 50 75 100 125 150 tj [] ivh0 [ma] charge current for vcc pin (ipre1) vs. junction temperature (tj) -10 -9 -8 -7 -6 -5 -4 -3 -50 -25 0 25 50 75 100 125 150 tj [] ipre1 [ma] shutdown threshold voltage (vccoff) vs. junction temperature (tj) 7 7.2 7.4 7.6 7.8 8 8.2 8.4 8.6 8.8 9 -50 -25 0 25 50 75 100 125 150 tj [] vccoff [v] startup threshold voltage (vccon) vs. junction temperature (tj) 12.5 13 13.5 14 14.5 15 15.5 -50 -25 0 25 50 75 100 125 150 tj [] vccon [v] uvlo on threshold voltage (vccon) vs. junction temperature (tj) 9 9.2 9.4 9.6 9.8 10 10.2 10.4 10.6 10.8 11 -50 -25 0 25 50 75 100 125 150 tj ( ) vccon (v) vcc : increasing fa5642
an - 0 64e rev.1. 3 a pril 201 2 18 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / latch mode supply current (icclat) vs. junction temperature (tj) 100 150 200 250 300 350 -50 -25 0 25 50 75 100 125 150 tj [] icclat [ua] operating-state supply current (iccop1) vs. vcc pin voltage (vcc) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 5 10 15 20 25 30 vcc [v] iccop1 [ma] operating-state supply current (iccop1) vs. junction temperature (tj) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 -50 -25 0 25 50 75 100 125 150 tj [] iccop1 [ma] startup device on voltage (vstrst) vs. junction temperature (tj) 8 8.2 8.4 8.6 8.8 9 9.2 9.4 9.6 9.8 10 -50 -25 0 25 50 75 100 125 150 tj [] vstrst [v] startup device off voltage (vstoff) vs. junction temperature (tj) 9.5 10 10.5 11 11.5 12 12.5 -50 -25 0 25 50 75 100 125 150 tj [] vstoff [v]
an - 0 64e rev.1. 3 a pril 201 2 19 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / 8 . basic operation (the values in the following description are typical values unless otherwise specified.) the basic operation of the power supply using ic is not switching operation with fixed frequency using an oscillator but switching with self - excited oscillation. this is shown in fig.1 s chematic circuit diagram and fig.2 waveform in the basic operation. t1 to t2 q1 turns on and then q1 drain current id ( current of primary windings of t1) begins to rise from zero. q1 current is converted into the voltage by rs and is input into is pin. t2 when the current of q1 get to the reference voltage of the current comparator that is fixed by the voltage of fb pin, a reset signal is input into rs flip - flop and q1 turns off. t2 to t3 when q1 turns off, then the windings voltage of the transformer turns over and the current i f is provided from the transformer into the secondary side through d1. t3 to t4 when the current from the transformer into the secondary side stops and the current of d1 get s to zero, the voltage of q1 turn s down rapidly due to the r esonance of the transformer inductance and the capacitor cd. at the same time the transformer auxiliary windings voltage vsub also drops rapidly. zcd pin receives this auxiliary windings voltage but then it has a little delay time because of cr circuit com posed with r zcd and c zcd on the way. t4 if zcd pin voltage turns down lower than the threshold voltage 5 0mv of bottom detection, a set signal is input into r - s flip - flop and q1 turns on again. if the delay time of cr circuit placed between the auxiliary w indings and zcd pin is adjusted properly , q1 voltage can be turn ed on at the bottom . t his operation make s the swit ching loss of turn on to the minimum . (return to t1) subsequently repeat from t1 to t4 and continue switching. fig.2 waveform in basic operation fig.1 schematic circuit diagram in basic ope ration out ( q 1 gate ) q 1 vds q 1 id d 1 i f vsub zcd pin current comparator out put ( reset ) 1 shot out put ( valley signal set ) t 1 t 2 t 3 t 4 60 mv bottom detection 1 shot ( 290 ns ) bottom skip control driver level shift zcd c 1 r 1 rs 2 3 s q r 1 5 out is fb d 1 vds vsub if set rset current comparator q 1 cd
an - 0 64e rev.1. 3 a pril 201 2 20 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / 9 . description of the function (the values in the following description are typical values unless otherwise specified.) (1) steady - state operation, bottom - skip operation, and burst operation ? steady - state operation, bottom - skip operation (f a5640/41/42/43/44/48 *fa5648:see spec. of p10 ) the on/off cycle, which is from turn - on of the driver signal to the end of fly - back voltage, is detected, and bottom - skip operations are performed at the time detected. since the relation between the on/off width and the number of times of bottom s kip operations is exhibited in the hysteresis as shown in fig. 4, waveform fluctuations can be prevented and transformer audible nois e can be decreased. fig . 5 shows the change image of the switching frequency to th e output electric power . fig . 6 shows the change image of the on/off width . fig.3 steady - state operation and bottom - skip operation timing chart vds bottom signal t < 10 us out pulse 10 us < t < 11 . 67 us load increase 11 . 67 us < t < 14 us 4 th 3 rd on / off pulse width 2 nd vds on / off pulse width bottom signal t > 9 us out pulse 9 us > t > 8 us 8 us > t > 7 us t < 7 us load decrease 1 st 3 rd 4 th 2 nd t > 14 us 1 th on - off width
an - 0 64e rev.1. 3 a pril 201 2 21 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / fig.4 on/off width at transfer to bottom - skip operation fig. 5 change image of switching frequency fig. 6 change image of on/off width 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 on-off width [us] bottom count [th] load decrease load increase 11.67us 0 50 100 150 0 20 40 60 80 100 output power [w] switching freq. [khz] load decrease load increase bottom skip 1st 2nd 3rd 4th 1st 2nd 3rd 4th 0 5 10 15 20 0 20 40 60 80 100 output power [w] on-off width [us] load decrease load increase bottom skip 1st 2nd 3rd 4th 1st 2nd 3rd 4th
an - 0 64e rev.1. 3 a pril 201 2 22 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / ? burst operation when the fb pin voltage decreases to lower than the pulse shutdown threshold voltage, switching is stopped. on the contrary, if the fb voltage increases to higher than the pulse shutdown threshold voltage, switching is resumed. overshoot a nd undershoot of the fb pin voltage occur over and under the pulse shutdown threshold voltage for mode switching. continuous pulses are issued during this overshoot period, and lo ng - cycle burst frequency is obtained during the undershoot period. the pulse shutdown threshold vol tage is switched to 0.45 v when input voltage is low, whereas it is switched to 0.35 v when input voltage is high, as input voltage compensation . fig. 7 burst operation at light load vthfb 01 = 0 . 45 v vthfb 02 = 0 . 35 v fb pin voltage pulse stop voltage out pin switching pulse heavy load light load ( burst switching )
an - 0 64e rev.1. 3 a pril 201 2 23 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / (2) startup circuit and auxiliary winding voltage w hen power is turned on, the current supplied from the startup circuit to the vcc pin through the vh pin charges the capacitor connected to the vcc pin to incr ease voltage. if the vcc pin voltage exceeds on threshold voltage 14 v or 10 v, the internal operation power is turned on, and the ic is start operating . at this time, if the voltage supplied from the auxiliary winding is higher than 9 v, the startup circu it is operated at the time of startup only, and after the startup, auxiliary winding voltage is used as power supply. meanwhile, if the auxiliary winding voltage is lower than 9v, the ic maintains operation within the vcc range between 9v and 11v by on/off of startup circuit. fig. 8 startup and shutdown (when auxiliary winding voltage is higher than 9v) fig. 9 startup and shutdown (when auxiliary winding voltage is lower than 9v) vcc startup circuit switching 11 v 9 v 8 v 14 v ac sw vcc startup circuit switching 11 v 9 v 8 v 14 v ac sw
an - 0 64e rev.1. 3 a pril 201 2 24 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / ( 3 ) operation under overload using the built - in timer, the duration of overload status of 200 ms or longer is detected, and switching is stopped forcibly. if the switching is stopped, supply of current from the auxiliary winding is eliminated, an d the vcc pin voltage reduces to 9 v or lower, the startup circ uit is operated , and the vcc is maintained within the range from 9 v to 11 v. if overload status continues for 200 ms or longer, the switching is stopped, and then after the elapse of 1400 ms, the switching is resumed. at that time, if the ov erload status persists, start and stop switching are repeated. if the load returns to normal, normal operation is resumed. at the time of startup, it is necessary to increase the output voltage to the settin g within the timer setting of 200 ms. since the operation is performed automatically using the built - in timer, even if external power is input directly to the vcc pin , operation is reset automatically. fig. 10 operation under overload (auto recovery typ e) 11 v 9 v 8 v 200 ms 3 . 3 v 200 ms 1600 ms 200 ms 1600 ms 14 v 200 ms 1600 ms vcc pin voltage start up circuit on / off signal olp timer output output pin switching pulse fb pin voltage olp timer operation active disabled on off normal load over load normal load
an - 0 64e rev.1. 3 a pril 201 2 25 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / timer l atch type (FA5644) using the built - in timer, the duration of overload status of 256 ms or longer is detected, switching is stopped, and latch mode is entered, with this state maintained. in a state in which switching is stopped due to overload latch, vcc is supplied from the startup circuit while operation is suspended. to reset the overload latch, it is necessary to interrupt the input voltage to stop the supply of vcc from the startup circuit, thus decreasing the off threshold voltage to 8.0 v or lower. at the time of startup, it is necessary to increase the output voltage to the setting within the timer setting of 256 ms. fig. 11 operation under overload ( timer latch type) 11 v 9 v 8 v 256 ms 3 . 3 v 256 ms 200 ms 1600 ms 14 v vcc pin voltage start up circuit on / off signal olp timer output output pin switching pulse fb pin voltage olp timer operation active disabled on off normal load over load
an - 0 64e rev.1. 3 a pril 201 2 26 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / (4) overvoltage protection function on the secondary side in ca se of overvoltage of output , the voltage of the auxiliary winding also rises . the zcd pin has the function of cycle - by - cycle detecting the voltage of the auxiliary winding of transformer . if the state in which the zcd pin voltage is 6.0 v or higher continu es for 60 ? s or longer, switching is stopped and the operation is latched - off . this state is maintained until the input voltage is interrupted, and the vcc decreases to the off threshold voltage of the uvlo. for example if switching is made at 40 khz, 60 ? s ? 40 khz = 2.4: detection of twice or more is required. (5) external latch - off function by pulling up the zcd pin to 6.0 v or higher for 60 ? s or longer, the ic is latched - off . this state is maintained until the input voltage is interrupted and vcc decr eases to the off threshold voltage of the uvlo. (6) compensat ing each threshold level by high - line voltage detection ( except fa564 2 ) by detecting the peak voltage of the vh pin , each threshold level is switched to compensate for high/low line voltage. the threshold level to be switched by high - line voltage include the pulse shutdown fb voltage, which is related to the pulse mode switching load, and the maximum input threshold voltage, which is the overcurrent limit level of the is pin . (7) minimum switchi ng frequency limitation and maximum on width limitation t he maximum on pulse width is limited to 24 ? s (fa5648:9 ? s ) to reduce the audible noise of the transformer when it is started and stopped. i n addition, fa5641 is integrated in minimum switching frequen cy that is limited at 25 khz to reduce audible noise more. see 10. (9) other advice on designing for details. (8) switching of overload protection levels due to external signal detection (standby - mode function ) (except fa5643 /48 ) by pulling up the volta ge of is pin to higher than the is pin standby detection voltage during the off period of the mosfet using external signals, overload protection levels can be switched. more specifically, by switching the maximum input threshold voltage, which is the overc urrent limit level of the is pin , the power can be limited to approximately 1/7 of the overload protection level of normal operation. this function is useful for limiting the power in standby mode, for example. (9) restart operation if the mosfet cannot b e turned on based on bottom detection of the zcd pin at the time of startup, restart operation is performed using a timer to forcibly turn on the mosfet. if the condition in which the out is l ow (mosfet is off) and the voltage of the zcd pin is below to in put threshold voltage (vthzcd2) 150 mv or lower, t he timer starts counting and the mosfet is turned on when the timeout from the last zcd trigger. ( 10 ) is pin timer latch function (fa5643) this ic has function in it that carries out latch shutdown instant ly when the voltage higher than 0.97 v is impressed to is pin to protect a transformer short circuit. this state is maintained until the input voltage is interrupted and vcc decreases to the off threshold voltage of the uvlo.
an - 0 64e rev.1. 3 a pril 201 2 27 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / 10 . how to use each pin and a dvice for designing (the values that appear in the following description ar e typical values, u nless otherwise specified.) (1) pin no. 1 (zcd pin ) function ( ) d etects the timing that mosfet is turned on . ( )performs latch - off protection by external signal s. ( )performs latch - off protection in case overvoltage on the secondary side. how to use ( ) turn on timing detection ? connection method connect the auxiliary winding of the transformer via the cr circuits, r1 and c1 (fig. 1 2 ). be careful the polarity o f the auxiliary winding. ? operation if the voltage of the zcd pin decreases to 6 0 mv or lower, the mosfet is turned on. the auxiliary winding voltage fluctuates significantly in both positive and negative voltage at the time of switching. to protect the i c from this voltage fluctuation, a clamp circuit is integrated . if the auxiliary winding voltage is positive, current is fed as shown in fig. 1 3 , and if it is negative, current is fed as shown in fig. 1 4 , to clamp the voltage of the zcd pin . in turning on based on bottom detection of the zcd pin is not possible at the time of startup, for example, restart operation is performed using timer to forcibly turn on the mosfet. if the out is l ow (mosfet is off) and the voltage of the zcd pin is below to inp ut thre shold voltage ( vthzcd2) 150 mv or lower, the timer starts counting, and if the time out time from the last trigger 25 ? s ( fa5641: 7.6 ? s ,fa5648:1 2 . 5 ? s), the mosfet is turned on . ( ) latch - off protection by external signals ? connection method pull up the zcd pin by external signals. figure 1 5 is a typical connection showing the overvoltage on the primary side. (constants are examples. check the operation with the actual power supp ly unit .) ? operation if the voltage of the zcd pin exceeds 6.0 v, and this state continues for 60 ? s or longer, latch - off operation is performed to stop output switching. once the latch - off operation is started, the vcc voltage is maintained by the startu p circuit to continue the latch - off operation. decrease the vcc to the off threshold voltage or lower to reset the latch operation. ( ) latch - off protection at overvoltage on the secondary side ? connection method the same as turn on timing in ( ) ? operation if the output voltage (vo) on the secondary side enters overvoltage state, the auxiliary winding voltage and zcd pin voltage als o increase. t his ic detects zcd pin voltage elapsed time of 4.5 ? s (fa5648:1.0 ? s ) after mosfet is turned off , and when the zcd pin voltage exceed 6.0v and this states continues for 60 ? s or longer, latch - off operation is performed to stop switching (fig. 1 6 ). once the latch operation is started, the vcc voltage is maintained by the startup circuit to con tinue the latch operation. decrease the vcc to the off threshold voltage of the uvlo or lower to reset the latch operation. fig. 1 2 zcd pin circuit fig. 1 3 clamp circuit (when auxiliary winding is in positive voltage.) fig. 1 4 clamp circuit (when auxiliary winding is in negative voltage.) fig. 1 5 primary side overvoltage protection circuit 1 30 k ? 7 . 5 v zcd c 1 r 1 cd r zcd 1 30 k ? 7 . 5 v zcd clamp current 1 30 k ? zcd clamp current - 0 . 8 v 1 6 vcc zcd 8 . 2 k 2 . 2 k 2 . 2 k 24 v 0 . 47 uf ? ^ ???
an - 0 64e rev.1. 3 a pril 201 2 28 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / advice for designing immediately before the mosfet is turned on, the mosfet drain - source voltage is resonated due to the transformer inductance and the resonance capacitor cd. adjust c1 to allow the mosfet to be turned on at the valley of this resonance (see figs. 1 7 and 1 8 ). since overvoltage threshold voltage is 5.7 v (min.), select resistance r1 not to allow the zcd pin voltage to exceed 5.7 v, or allow the zcd pin current to exceed the absolute maximum rating, in normal operation, ensuring that the following calculation formulae are satisfied. where, v zcd : zcd pin voltage at normal operatio n v thovp : zcd pin overvoltage threshold level (6 v ) vn s : line voltage s econdary winding of transformer at normal operation (vo ? vf) v ovp : output voltage to be subjected to overvoltage latch - off where, vn sub : line voltage of aux iliary winding of transformer n sub : number of turns of auxiliary windings of transformer n s : number of turns of secondary windings of transformer using the formula , r1 is found to be w here, r zcd : internal resistance of zcd pin (30 k ? ) if the capacitan ce of capacitor c1 is to be increased to prevent malfunction due to surge, for example, it may be necessary to decrease the resistance r1 for bottom detection of the auxiliary winding. if the overvoltage detection level decreases as a result, add resistanc e r2 for adjustment. in this case, the following formula applies: since the source current of the zcd pin input current (absolute maximum rating) is ? 2.0 ma, +3.0ma the following formula must be satisfied at the same time: where, i s o zcd : zcd pin input current (source current = ? 2.0 ma) i s i zcd : zcd pin input current (sink current = +3.0 ma) v out (max) : maximum output voltage generally, r1 is around several tens k ? , whereas c1 is around several tens pf. if timing of bottom detection is ok, c1 need not b e connected. add schottky diode between zcd - gnd as shown in figure 1 8 when the terminal zcd input current is not filled even if r1 is appropriately adjusted. if r1 and c1 constants are not appropriate , overvoltage pr otection may not function properly. figu re 1 9 shows the zcd pin waveform at the time of overvoltage protection. with the upper zcd pin waveform, overvoltage on the secondary side is detected properly, and latch - off is performed by fault protection . meanwhile, with the lower zcd pin waveform, pro tective function is not opera ted because the threshold voltage is not reac hed in 4.5 ? s (fa5648:1.0 ? s) . in this case, adjust r1 and c1. fig. 1 6 zcd pin waveform at overvoltage on the secondary side fig. 1 7 vds waveform fig. 1 8 zcd pin resistance r1 cal culation v zcd = v thovp vn s / v ovp vn sub = vn s n sub / n s v zcd = vn sub r zcd / ( r 1 r zcd ) r 1 = vn sub r zcd / v zcd r zcd r 1 = r zcd r 2 r zcd + r 2 vn sub v zcd 1 r 1 > 2 v ac ( max ) n sub / n p / i sozcd r 1 > v out ( max ) n sub n s 7 . 5 / i sizcd vo zcd pin 0 v 0 v 6 . 0 v 4 . 5 us 60 us latch vds 1 30 k ? 7 . 5 v zcd c 1 r 1 cd r zcd v ns v o v f ns np nsub v nsub v zcd r 2 d 1
an - 0 64e rev.1. 3 a pril 201 2 29 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / (2) pin no. 2 (fb pin ) function ( )input feedback signals from the error amplifier on the secondary side. ( )detects overload status. ( )stops switching for burst operation. how to use ( ) feedback signal input ? connection method connect the opto coupler corrector to this pin will allow reguration . at the same time, to prevent generation of noise, connect a capacitor in parallel to the optocoupler (fig. 20 ). ? operation pin no. 2 is b iased from the ic internal power supply via the resistance. the fb pin voltage is level - shifted and input into the current comparator to provide the threshold voltage of the mosfet current signals to be detected with the is pin . ( ) overload detection ? connection method the same as the feedback signal input in ( ). ? operation i n case of overload, the output voltage decreases to lower than the setting, therefore the fb pin overshoots to the high side. this state is detected to jud ge overload status. the threshold voltage for overload judgment is 3.5 v. by the automatic recovery function , overload status brings about hiccup operation, and once the overload state is reset, operation is automatically resumed. see 9. (3) operation und er overload for details of operation. ( ) stopping switching for burst operation ? connection method the same as feedback signal input in ( ) ? operation fb pin voltage decreases under light load. if this voltage decreases to threshold voltage of stopping on - pulse or low er, switching is stopped , and switching is resumed if the voltage increases to the threshold voltage of stopping on - pulse or higher . by repeating this operation, burst operation is achieved. to undershoot the fb pin voltage significantly at the time of b urst operation, the intern al fb pin resistance is switched (fig. 20 ). to co mpensate the dependence of load point for enter ing burst operation on the high - line voltage, the pulse shutdown fb threshold voltage is switched to 0. 3 5 v for high line voltage, and 0. 4 5 v for low line volta ge. fig. 1 9 zcd pin waveform at overvoltage advice for designing the fb pin provides threshold voltage of the current comparator. if noise is added to the pin , output pulse fluctuation may result. to prevent generation of noise, a capacitor having th e capacitance o f approximately 1000 pf to 0.01 ? f is connected for use as shown in fig. 20 . fig. 20 fb pin circuit 0 v 6 . 0 v 6 . 0 v 0 v 4 . 5 us 2 24 k ? 4 . 8 v fb 1000 pf 0 . 01 uf 216 k ? / 108 k ?
an - 0 64e rev.1. 3 a pril 201 2 30 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / (3) pin no. 3 (is pin ) function ( ) detects and limits the current value of the mosfet. ( ) switches the maximum threshold voltage of current limit by external signals. (standby mode function) (except fa5643) ( ) detection of transformer short circuit protection how to use (fa5643) ( ) current detection and current limiting ? connection method connect a current detecting resistor rs between the mosfet source pin and the gnd. the current signals of the mosfet generated in the resistor are input (fig. 2 1 ). ? op eration the current signals of the mosfet input to the is pin is then input to the current comparator, and if it reaches the threshold voltage determined by the fb pin , the mosfet is turned off . this fb pin voltage fluctuates due to the feedback circuit fr om the output voltage to control the mosfet current. in addition, since the maximum input threshold voltage is also input to the current comparator, the mosfet current is limited by the current equivalent to this voltage even in an emergency state such as transient state at the time of startup or overload status. if overload state continues, the latch - off stop is performed by the overload protection function. generally, t he output current value that is stopped in the latch - off mode varies depending on the h igh - line voltage, and there may be a case in which the higher the line voltage, the larger the output current that is stopped in the latch mode. to compensate the dependency of overload detection level on the line voltage, the maximum input threshold volta ge is switched between 0.5 v (low line voltage) and 0.45 v (high line voltage). ( ) switching of current limiting maximum threshold voltage by external signals (standby mode function, except ? connection method fa5643) as shown i n fig. 2 2 , a diode, current limiting resistor, transistor switch, op tocoupler, etc. are added between the auxiliary winding and the is pin . ? operation while the mosfet remains on, mosfet current signals are kept input to the is pin for comparison with the threshold voltage that is determined by the fb pin . with this ic, is pin voltage level is detected during this off period. by increasing the is pin voltage to 0.55 v, which is the is pin standby detection voltage, or higher within 2 ? s after the mosfet is turned off , the maximum input threshold voltage of the is pin is switched. in this case, the detection level is decreased to approximately 1/7 of that of normal o peration . b ut it is necessary to confirm output power in actual power supply unit because the output power may vary with specification of transformer and circuit constant . for example, the power of the power supply is limited in standby mode. specifically, the maximum input threshold voltage is switched between 0.15 v (low line voltage ) and 0. 1 v (high line voltage ). if low signals are input from the external signal, transistor tr1 and the op tocoupler are set to off, and transistor tr2 is brought into continued state, and the is pin is subjected to the effect of the auxiliary winding voltage. the auxiliary winding voltage remain positive while the mosfet is set to off, and negative while it is set to on, and thanks to the function of diode d1, the is pin voltage is increased to positive side only during the period in which the mosfet remains of f. fig. 2 1 is pin circuit fig. 2 2 power limiting circuit and waveform at standby detection 3 rs is current comparator is vcc rs 6 3 vout d 1 d 2 external switch signal tr 2 tr 1 r 3 normal standby standby detection voltage 0 . 55 v ( typ .) is pin delay 2 . 0 us
an - 0 64e rev.1. 3 a pril 201 2 31 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / ( ) detection of transformer short circuit protection ? connection method (fa5643) the s ame as current detection and current limiting in ( ) . ? operation this ic has function in it that carries out latch shutdown instantly when the voltage higher than 0.97 v is impressed to is pin to protect a transformer short circuit. this function also carries out instantly latch shutdown except a tr ansformer short circuit when the voltage higher than 0.97 v is impressed to is pin. therefore if the high voltage is impressed to the input side such as lightning surge, the protection operation may carry out latch shutdown. in such a case the values of is pin filter ris, c is and a surge protection element for the input line should be readjusted. ( see fig. 23. ) advice for designing (1) insertion of a filter si nce this ic has a leading edge blanking (minimum on width: 290 ns), malfunction due to surge c urrent gen erated at the mosfet is switched on does not occur . however, if the surg e current generated at the leading edge of out is large, or external noise is added, malfunction may occur . in such cases, add a cr filter to the is pin as shown in fig. 2 4 . the filter constant depends on the magnitude of the noise , but as the time constant of ris ? cis, about 500 ns or less is recommended. note, however, the overload detection level and the load level of starting burst operation may vary , thus audible noise may be gene rated or standby power may vary. pay special attention to the above phenomena. ( 2) burst operation point adjustment 1 under light load if burst operation is started under heavy load, the audible noise may be generated at transformer . to decrease the burst point slightly, add resistor r4 between the is pin and the out pin (fig. 2 5 ). if r4 is connected, the positive bias voltage is applied to the is pin voltage when the mosfet is turned - on , and consequently, the fb pin voltage also remains high level . since burst operation occurs if the fb pin voltage decrease to 0.45 v (at low line voltage) or lower, burst operation does not tend to occur if the fb pin voltage remains high. even if a resistor is added between the is pin and the out pin , the effect of resisto r r4 may not be obtained if ris is small. in this case, decrease cis and increase ris, while fixing the time constant of the filter (ris = 470 ? is recommended when r4 is added). note, however, that the standby power may increase, or overload detection lev el may vary. with this ic, though the dependency of overload detection level on line voltage has been compensated , this ratio may deviate. c onfirm there is no problem in application enough. (3) burst operation point adjustment 2 under light load to all ow bust operation to occur under slightly heavier load, thus to improvement the efficiency under light load, on condition that there is no transformer audible noise problem, add resistor r5 between the is pin and the out pin (fig. 2 6 ). note, however, that the overload detection level varies in this case also. with this ic, though the dependency of overload detection level on line vo ltage has been compensated, this ratio may deviate . c onfirm there is no problem in application enough. fig. 2 3 transf ormer short circuit protection fig. 2 4 is pin filter fig. 2 5 burst operation point adjustment 1 fig. 2 6 burst operation point adjustment 2 cis gnd is 3 4 ris rs c 1 short 3 rs is current comparator ris cis gnd is 3 ris rs cis 5 out r 4 4 gnd is 3 4 ris r 5 rs c 1 6 vcc
an - 0 64e rev.1. 3 a pril 201 2 32 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / (4) switching of current limiting maximum threshold voltage by external signals (except fa5643 /48 ) d iodes d1 and d2 in fig. 2 2 can share parts with the diode connected between the vcc pin and the auxiliary winding. while the mosfet is turned - off, the voltage of auxiliary windings is depended on output voltage on the secondary side and ratio of the number of turns of secondary windings and number of turns of auxiliary windings. as the pull - up level of the is pin voltage, determine the value of r3 so that the is pin voltage reaches is pin standby detection voltage 0.55 v, or higher within 2 ? s after the turn off. in th is case, if ris is small, the is pin voltage may not increase. therefore, adjust the constant of the f ilter, following the description in (2) burst operation point adjustment 1 under light load. diode d2 is added to prevent heating of the mosfet in the e vent diode d1 is short - circuited, causing negative voltage to be applied to the is pin and allowing the on width to increase abnormally. (5) fine adjustment of overload detection level the overload detection level is determined by the value of resistor rs in principle. to fine - tune the level, add resistor r6 as shown in fig. 2 7 to input the voltage divided by resistors ris and r6 into the is pin. fig. 2 7 fine adjustment of overload detection level 3 rs is ris cis r 6
an - 0 64e rev.1. 3 a pril 201 2 33 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / (4) pin no. 4 (gnd pin ) func tion pin no. 4 serves as the basis of the voltage of each part of the ic. (5) pin no. 5 (out pin ) function drives the mosfet how to use ? connection method connect pin no. 5 to the mosfet gate (figs. 2 8 , 2 9 , and 30 ). ? operation while the mosfet remains o n, it is in high state, and vcc voltage is output. while the mosfet remains off, it is in low state, and 0 voltage is output. advice for designing connect the gate resistor to limit the current fed to the out pin or prevent vibration of gate pin voltage. a djust the gate resistor not to exceed the ic output current rating of 0.25 a (source) and 0.5 a (sink). (6) pin no. 6 (vcc pin ) function supplies for the ic. how to use ? connection method generally, the pin is connected the auxiliary winding of the tran sformer which is rectified and smoothed (fig. 31 ). the auxiliary winding that can be connected to the zcd pin can be shared. ? operation set the voltage to be supplied from the auxiliary winding within the 11 to 26 v range (recommended operation condition) in normal operation. since the startup circuit is operated when the vcc pin voltage decreases to the startup current res tart voltage, 9 v, or lower, the vcc pin voltage is recommended to be used by 11 v or higher because the startup circuit is not operate d. it is also possible to operate the ic not by using the auxiliary winding but using the current supplied from the startup circuit. however, standby power increases and heating of ic also increases in these cases . consequently, to achieve low standby pow er, it is recommended to supply vcc from the auxiliary winding. at the same time, if the startup circuit only is used for st artup, the mosfet to be driven must be selected carefully because there is a limit in current to be supplied . fig. 2 8 out pin cir cuit (1) fig. 2 9 out pin circuit (2) fig. 30 out pin circuit (3) fig. 31 vcc circuit 5 6 4 driver out vcc gnd 5 6 4 driver out vcc gnd 5 6 4 driver out vcc gnd 1 6 vcc zcd c 2 c 1 r 1
an - 0 64e rev.1. 3 a pril 201 2 34 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / advice for designing (1) connection of the bypass capacitor since l arge current is fed to the vcc pin when the mosfet is drive n , relatively large noise tends to be generated. in addition, noise is also generated from the current supplied by the auxiliary winding. if this noise is large, malfunction of the ic may result. to minimize the noise that is generated at the vcc pin , add a bypass capacitor c2 (0.1 ? f or hi gher) adjacent to the vcc pin of the ic, between vcc and the gnd, as shown in fig. 31 , in addition to the electrolytic capacitor. (2) adjustment of power supply voltage input range the recommended suppl ied voltage range is 11 v to 26 v. when the load is light , the vc c pin voltage decreases, whereas when the load is heavy, the voltage increases, thus deviating from the power supply voltage range. in such cases, change the resistor between the vcc pin and the diode to adjust the voltage. also, by adding beads co re at the foot of the resistor, voltage fluctuation may be suppressed. if the above methods do not work, it is recommended to change the secondary winding and the auxiliary winding of the transformer to bifilar winding. (3) when power is supplied directly to the vcc pin when directly supplying power to the vcc pin without using vh pi n , open the vh pin or short - circuit the vh pin and the vcc pin for use. if the vh pin is connected to the gnd, leakage current may be generated. (7) pin no. 7 (n.c.) since thi s pin is placed adjacent to the high - voltage pin , it is not connected to inside the ic. (8) pin no. 8 (vh pin ) function ( ) supplies startup current. ( ) detects and compensates by the high - line voltage. (except fa5642) how to use ( ) supply startup c urrent. ? connection method connect the pin to the high - voltage line. in this case, if connection is to be made after rectification, connect it via a resistor of several k ? (fig. 3 4 ). on the other hand, if connection is to be made before rectification, con nect it to the high - voltage line via a resistor of several k ? and a diode (figs. 3 2 and 3 3 ). ? operation this ic, which integrates a startup circuit having withstand voltage of 500 v, achieves low power consumption. figure 3 2 presents a typical connecti on method, in which the vh pin is connected to the half - wave rectification waveform of the ac line voltage. with this method, the startup time is the longest of the three connection methods. in addition, since current supply from the vh pin is interrupted if the ac line voltage is interrupted after the ic enters the latch - off mode, the latch - off mo de can be reset in a period of time as short as several seconds. fig. 3 2 vh pin circuit ( 1 ) with the connection shown in fig. 3 3 , the vh pin is connected to th e full wave rectification waveform of the ac line voltage. the startup time of this method is approximately half of that of the half - wave rectification shown in fig. 3 2 . in addition, by interrupting the ac line voltage, the time required for resetting the latch mode is as short as the case shown in fig. 3 2 . but this connection method may malfunction when the model which is integrated line voltage compensation is used, so fa5642 only is recommended this connection. fig. 3 3 vh pin circuit ( 2 ) startup circuit on/off signal startup circuit on/off signal 8 6 start ? on / off ? vh vcc 8 6 start ? on / off ? vh vcc
an - 0 64e rev.1. 3 a pril 201 2 35 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / with the met hod shown in fig. 3 4 , the vh pin is connected after the ac line voltage is rectified and smoothed. the startup time of this method is the shortest of the three connection methods. however, since the voltage charged in the bulk capacitor is applied to the v h pin even if the ac line voltage is interrupted after the ic enters the latch - off mode, longer time is required to reset the latch - off mode. note that several minutes are required to reset the latch - off mode after the ac line is interrupted, although the duration depends on the operating conditions. if power is turned on, the capacitor connected to the vcc pin i s charged due to the current supplied from the startup circuit to the vcc pin via the vh pin , and the vcc voltage increases. when the on threshold voltage of 14 v of the low - voltage malfunction prevention circuit (uvlo) is exceeded, the internal supply is started to operate the ic. if vcc is not supplied from the auxiliary winding, the startup circuit is stopped . meanwhile, if power is not supplied from the auxiliary winding, the curre nt supplied from the startup circuit is used for the normal operation of the ic. if vcc is supplied only from the startup circuit, without the supply from the auxiliary winding, the standby power increases, and the heat ing of the ic may increase. consequently, to keep the standby power at low level, it is desirable to supply vcc from the auxiliary winding. at the same time, if the startup circuit only is used for startup, there is a limit in current to be supplied. conse quently, the mosfet to be driven must be selected carefully. the current fed from the vh pin to the vcc pin is approximately 8 ma when vcc = 6.5 v. note that when vcc = 0 v, the current decreases to 0.7 ma to cope with abnormal state such as short circuit between pin s. ( ) the peak voltage of the line voltage is detected to sub ject it to high/low line voltage compensation . (except ? connection method fa5642) the same as the method of supplying startup current in (i) ? operation if voltage after rectification is input to the vh pin , each threshold level is switched at 22 6 v when the vh pin voltage is increasing, and 212 v when it is decreasing. if half - wave and full - wave rectification waveforms are input, it is switched at 160 v rms . the in put detection switching delay time is 30 ms. the threshold level for switching based on input voltage in clude the pulse shutdown fb voltage, which is related to the burst operation , and the maximum input threshold voltage, which is the over load li mit level of the is pin . fig. 3 4 vh pin circuit ( 3 ) advice for designing (1) startup resistor to prevent damage to the ic due to surge voltage of the ac line, it is recommended to connect a startup resistor whose resistance within the 2 k ? to 10 k ? ra nge to the vh pin in series. startup time or startup voltage cannot be adjusted using this startup resistor. note that a resistor having too large resistance may result in inability to startup. (2) to supply power directly to the vcc pin to supply power d irectly to th e vcc pin without using a vh pin , open the vh pin or short - circuit the vh and the vcc pin s. if the vh pin is connected to the gnd, leakage current may be generated. 8 6 start ? on / off ? vh vcc
an - 0 64e rev.1. 3 a pril 201 2 36 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / (9) other advice on designing (1) surge that occurs at startup due to the mi nimum switching frequency limiting our lineup includes the one that the minimum switching frequency and the maximum on width are set with this ic t o reduce audible noise at the time of starting /stopping . however, due to this minimum switching frequency fu nction, there is a period in which the ic is operated in continuous conduction mode at startup, which may result in increased surge voltage of the diode on the secondary side. please consider using the one that this minimum switching frequency limiting fun ction was not integrated if the serge of the diode is a problem. (2) switching frequency at the time of bottom skip this ic detects on/off width using the zcd pin , thus controlling the number of times of bottom skips. bottom skip is performed up to the p oint where the ic is turned on at the four th bottom depending on the load. at this time, depending on the specifications of the power supply or design conditions of the transformer, the switching frequen cy at the time of bottom skip may be decreased to 40 khz or lower. if this frequency interferes with other devices, causing problems, for example, adjust the resonance capacitor connected between the drain and the source of the mosfet. if the capacitance is reduced, the resonance frequency increases, allowin g the switching frequency at bottom skip to increase. (3) preventing malfunction due to negative voltage of the pin if large negative voltage is applied to each pin of the ic, the parasitic devices within the ic may be operated , thus causing malfunction. c onfirm that the voltage of - 0.3 v or less is not applied to each pin . the vibration of the voltage generated after the mosfet is turned - off may be applied to the out pin through the parasitic capacitance, resulting in a case in which negative voltage is a pplied to the out pin . in addition, negative voltage may be applied to the is pin due to the vib ration of surge current generated at the turn - on of the mosfet. in such cases, connect a schottky diode between each pin and the gnd. the forward voltage of the schottky diode can suppress the negative voltage at each pin . in this case, use a schottky diode whose forward voltage is low. figure 3 5 is a typical connection diagram where a schottky diode is connected to the out pin . (4) loss calculation to use the ic within its rating, it is necessary to confirm the loss of the ic. however, since it is difficult to measure the loss directly, the method of confirming the loss by calculation is shown below. if the voltage applied to the vh pin is defined as vvh, the current fed to the vh pin during operation as i v hrun, power supply voltage as vcc, supply current as iccop1, gate input charge of the mosfet to be used as qg, and switching frequency as fsw, the total loss pd of the ic can be calc ul ated using the following formula. a rough value can be found using the above formula, but note that pd is slightly larger than the actual loss value. also note that each specific characteristic value has temperature characteristics or variation. example: if the vh pin is conne cted to a half - wave rectification waveform with ac 100 v input, the average voltage to be applied to the vh pin is approximately 45 v. in this state, assume that vcc = 15 v, qg = 80 nc, and fsw = 60 khz (when tj = 25 ? c). since i v hrun = 30 ? a and iccop1 = 0 . 85 ma from the specifications, the standard ic loss can be calculated as follows: pd 15v x (0. 85 ma + 80nc x 60khz) + 45v x 30 a 86. 1 mw fig. 3 5 negative charge prevention circuit p d v c c ( i c c o p 1 + q g f s w ) + v v h i v h r u n gnd out 5 4 sbd rg
an - 0 64e rev.1. 3 a pril 201 2 37 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / 1 1 . precautions for pattern design (1) precautions for pattern des ign in order to prevent the malfunction of the control ic (unstable voltage, unstable waveform, latch - off , etc.) caused by the surge voltage (noise) when a current is applied to the pattern on the minus side because of a principal current, a lightning surg e test, an ac line surge test, and a static electricity test , consider the following contents when designing the pattern. the power supply has the following current paths: 1) a principal current applied from the electrolytic capacitor to the primary windi ng of the transformer, the mosfet, and the current sensing resistor after ac power supply rectification 2) a rectified current applied from the auxiliary winding of the transformer to the electrolytic capacitor; a drive current a pplied from the electrolyti c capacitor to the control ic and the mosfet gate. 3) a control current of the control ic for output feedback or the like 4) filter and surge currents applied between the primary and secondary sides ? separate the patterns on the minus side in 1) to 4) to avoid interference from each other. ? to reduce the surge voltage of the mosfet, minimize the loop of the principal current path. ? install the electrolytic and film capacitors between the vcc pin an d the gnd in a closest position to each pin in order to connect them at the shortest distance. ? install the filter capacitors for the fb, is, and zcd pin s and the like in a closest position to each pin in order to connect them at the shortest distance. es pecially, c onnect the patterns on the negative side of the fb and is pin s to the gnd pin of the ic, separately from other patterns, keeping the wiring as short as possible. ? avoid installing the control circuit and pattern with high impedance directly bel ow the transformer. fig.3 6 pattern design image 5 6 ac input output cn 2 1 4 8 7 6 5 1 2 3 4 lat fb is gnd out vcc ( nc ) vh principal current drive current filter and surge current control current
an - 0 64e rev.1. 3 a pril 201 2 38 fa5640/41/42 /43/44/48 fuji electric co., ltd. http://www.fujielectric.co.jp/products/semiconductor / 12. example of application circuit the typical application circuit shown here provides specifications common to each ic series. note: this application circu it is a reference material for describing typical usage of this ic, and does not guarantee the operation or characteristics of the ic. 2 5 7 8 1 3 , 1 4 , 1 5 , 1 6 9 , 1 0 , 1 1 , 1 2 1 a c 8 5 t o 2 6 4 v 2 4 v / 4 a 9 6 w f 1 0 . 4 7 u 4 a , 8 m h 0 . 2 2 u h s 1 d 1 0 x b 6 0 h 6 0 0 v , 1 a 4 . 7 k 2 0 0 v , 1 a 2 2 4 7 4 7 0 u 0 . 1 u 1 0 0 k 1 k v , 0 . 5 a t 1 n p : n s : n b = 4 0 : 1 2 : 1 0 l p = 1 7 6 u h 2 2 0 0 p t r 1 f m v 1 1 n 7 0 e 7 0 0 v / 1 1 a 0 . 1 1 0 k 4 0 0 v , 1 a 4 . 7 1 0 0 u 1 0 0 0 p p c 1 b 1 0 0 0 p 1 0 p i c 1 4 7 0 p 2 2 y g 9 0 6 c 2 r 2 0 0 v / 2 0 a 1 5 0 0 u 1 5 0 0 u c 2 3 0 . 1 u h s 2 0 . 1 u 1 . 5 k 4 . 7 k p c 1 a t l p 4 2 1 f g r 1 3 0 k 0 . 0 4 7 u 4 7 k 1 5 k c n 2 c n 1 h a 1 7 4 3 2 h u p 2 2 0 0 p 2 2 0 0 p 5 6 k f b 4 . 7 k f b 2 2 0 p 4 7 0 p 2 p 1 p 3 p 4 r v 1 3 5 1 2 3 4 1 m 1 m f a 5 6 4 0 8 7 6 5 1 2 3 4 z c d f b i s g n d o u t v c c ( n c ) v h 0 . 1 u 5 1 0 5 . 1 k 3 4 3 9 k s b d s b d s b d

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